In integrated circuits, there is a trend toward a higher device density to increase the number of devices per unit area. Device density is increased by making individual devices smaller and placing the devices closer together. Device dimensions (termed feature size or design rules) have decreased well into the sub-micron regime and continue to become smaller. There is a challenge in today's semiconductor manufacturing industry to continue to decrease feature sizes and also to decrease the distance between devices in a commensurate fashion.
Currently, the majority of MOS (metal oxide semiconductor) transistors have a planar configuration, with the direction of current flow parallel to the plane of the substrate surface on which the transistor is formed. Although there is a need to decrease the size of these devices to achieve increased device density, fabricating these small devices becomes increasingly difficult. In particular, lithography becomes extremely difficult as device dimensions decrease to less than the wavelength of the radiation used to delineate an image of a pattern in radiation-sensitive materials such as photoresists commonly used in the industry.
Vertical device structures have been developed of late, and continue to be developed as alternatives to the more space-consuming planar device configuration. Such devices include a transistor having a channel that is orthogonal to the surface on which it is formed. Such a device is called a vertical transistor because the length of the channel is orthogonal to the substrate surface and includes source/drain regions offset vertically from each other. The transistor gate may surround the channel. Vertical transistor configurations and methods for forming the same are described in U.S. Pat. No. 6,027,975, “Process for Fabricating Vertical Transistors”, and in U.S. Pat. No. 6,197,641, “Process for Fabricating Vertical Transistors”, the contents of each of which are hereby incorporated by reference for all purposes as if set forth in their entirety.
Although vertical MOSFETs (metal oxide semiconductor field effect transistors) can be packed more densely than planar MOSFETs, the processing issues for the vertical transistors are not trivial. Processes that make it easier and more efficient to fabricate vertical transistors, and processes that produce superior and high-quality transistors, are therefore desired.
Vertical transistors typically have vertical channels that include non-planar surfaces, convex corners, or both. It is therefore especially critical to form high-quality gate oxides on these transistor channels since oxide films formed on curved surfaces and surfaces with convex corners are particularly susceptible to stress-related defects and even dislocations. Growth induced stress typically leads to defects, especially in the interfacial region between the oxide film and the substrate surface on which the oxide film is being formed. Among other problems, this may result in undesirable mass transport paths and leakage currents. Stated generally then, such non-planar surfaces are more prone to higher defect densities and interface trap densities. It is therefore desirable to form high-quality oxide films on non-planar surfaces in general, and particularly on vertical transistor channels which typically include curved surfaces, convex corners, or both.